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lt 3042 1 3042fa for more information www.linear.com/lt3042 typical application features description 20v, 200ma, ultralow noise, ultrahigh psrr rf linear regulator the lt ? 3042 is a high performance low dropout linear regulator featuring lt c s ultralow noise and ultrahigh psrr architecture for powering noise sensitive rf applications. designed as a precision current reference followed by a high performance voltage buffer, the lt3042 can be easily paralleled to further reduce noise, increase output current and spread heat on the pcb. the device supplies 200 ma at a typical 350 mv dropout voltage. operating quiescent current is nominally 2 ma and drops to <<1 a in shutdown. the lt3042s wide output voltage range (0 v to 15 v) while maintaining unity- gain operation provides virtually constant output noise, psrr, bandwidth and load regulation, independent of the programmed output voltage. additionally, the regulator features programmable current limit, fast start-up capa- bility and programmable power good to indicate output voltage regulation.the lt3042 is stable with a minimum 4.7 f ceramic output capacitor. built-in protection includes reverse battery protection, reverse current protection, internal current limit with foldback and thermal limit with hysteresis. the lt3042 is available in thermally enhanced 10- lead msop and 3mm 3mm dfn packages. power supply ripple rejection applications n ultralow rms noise: 0.8v rms (10hz to 100khz) n ultralow spot noise: 2nv/ hz at 10khz n ultrahigh psrr: 79db at 1mhz n output current: 200ma n wide input voltage range: 1.8v to 20v n single capacitor improves noise and psrr n 100 a set pin current: 1% initial accuracy n single resistor programs output voltage n high bandwidth: 1mhz n programmable current limit n low dropout voltage: 350mv n output voltage range: 0v to 15v n programmable power good n fast start-up capability n precision enable/uvlo n parallelable for lower noise and higher current n internal current limit with foldback n minimum output capacitor: 4.7f ceramic n reverse battery and reverse current protection n 10- lead msop and 3mm 3mm dfn packages n rf power supplies: plls, vcos, mixers, lnas n very low noise instrumentation n high speed/high precision data converters n medical applications: imaging, diagnostics n precision power supplies n post-regulator for switching supplies l , lt , lt c , lt m , linear technology and the linear logo are registered trademarks of linear technology corporation. patents pending. all other trademarks are the property of their respective owners. frequency (hz) 40 psrr (db) 80 120 60 100 10 100 10k 100k 1m 10m 3042 ta01b 20 1k 30 70 110 50 90 v in = 5v r set = 33.2k c set = 4.7f c out = 4.7f i l = 200ma +C 100a in en/uvpg gnd out lt3042 ilim pgfb 450k 4.7f 4.7f v in 5v 5% 200k 4.7f v out 3.3vi out(max) 200ma 50k 3042 ta01a 499 33.2k set outs downloaded from: http:///
lt 3042 2 3042fa for more information www.linear.com/lt3042 pin configuration absolute maximum ratings in pin voltage ......................................................... 22 v en / uv pin voltage .................................................. 22 v in - to - en / uv differential .......................................... 22 v pg pin voltage ( note 10) ............................... C0.3 v, 22v ilim pin voltage ( note 10) ............................... C0.3 v, 1v pgfb pin voltage ( note 10) ........................... C0.3 v, 22v set pin voltage ( note 10) .............................. C0.3 v , 16 v set pin current ( note 7) .................................... 20 ma outs pin voltage ( note 10) ........................... C0.3 v , 16 v outs pin current ( note 7) ................................. 20 ma out pin voltage ( note 10) ............................. C0.3 v , 16 v (note 1) top view 11 gnd dd package 10-lead (3mm 3mm) plastic dfn 10 96 7 8 45 3 2 1 out outs gndset pgfb inin en/uv pg ilim t jmax = 150c, ja = 34c/w, jc = 5.5c/w exposed pad (pin 11) is gnd, must be soldered to pcb 12 3 4 5 inin en/uv pg ilim 109 8 7 6 out outs gndset pgfb top view 11 gnd mse package 10-lead plastic msop t jmax = 150c, ja = 33c/w, jc = 8c/w exposed pad (pin 11) is gnd, must be soldered to pcb order information lead free finish tape and reel part marking* package description temperature range lt3042edd#pbf lt3042edd#trpbf lgsj 10-lead (3mm 3mm) plastic dfn C40c to 125c lt3042idd#pbf lt3042idd#trpbf lgsj 10-lead (3mm 3mm) plastic dfn C40c to 125c lt3042hdd#pbf lt3042hdd#trpbf lgsj 10-lead (3mm 3mm) plastic dfn C40c to 150c lt3042mpdd#pbf lt3042mpdd#trpbf lgsj 10-lead (3mm 3mm) plastic dfn C55c to 150c lt3042emse#pbf lt3042emse#trpbf ltgsh 10-lead plastic msop C40c to 125c lt3042imse#pbf lt3042imse#trpbf ltgsh 10-lead plastic msop C40c to 125c lt3042hmse#pbf lt3042hmse#trpbf ltgsh 10-lead plastic msop C40c to 150c lt3042mpmse#pbf lt3042mpmse#trpbf ltgsh 10-lead plastic msop C55c to 150c consult lt c marketing for parts specified with wider operating temperature ranges . * the temperature grade is identified by a label on the shipping container . consult lt c marketing for information on nonstandard lead based finish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ out - to - outs differential ( note 14) ....................... 1.2 v in - to - out differential ............................................. 22 v in - to - outs differential ........................................... 22 v output short - circuit duration .......................... indefinite operating junction temperature range ( note 9) e -, i- grade ........................................ C40 c to 125 c h- grade ............................................ C40 c to 150 c mp - grade ......................................... C55 c to 150 c storage temperature range .................. C65 c to 150 c lead temperature ( soldering , 10 sec ) mse package ................................................... 300 c downloaded from: http:///
lt 3042 3 3042fa for more information www.linear.com/lt3042 electrical characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. parameter conditions min typ max units minimum in pin voltage (note 2) i load = 200ma, v in uvlo rising v in uvlo hysteresis l 1.78 75 2 v mv set pin current (i set ) v in = 2v, i load = 1ma, v out = 1.3v 2v < v in < 20v, 0v < v out < 15v, 1ma < i load < 200ma (note 3) l 99 98 100 100 101 102 a a fast start-up set pin current v pgfb = 289mv, v in = 2.8v, v set = 1.3v 2 ma output offset voltage v os (v out C v set ) (note 4) v in = 2v, i load = 1ma, v out = 1.3v 2v < v in < 20v, 0v < v out < 15v, 1ma < i load < 200ma (note 3) l C1 C2 1 2 mv mv line regulation : ?i set line regulation: ?v os v in = 2v to 20v, i load = 1ma, v out = 1.3v v in = 2v to 20v, i load = 1ma, v out = 1.3v (note 4) l l 0.5 0.5 2 3 na/v v/v load regulation: ?i set load regulation: ?v os i load = 1ma to 200ma, v in = 2v, v out = 1.3v i load = 1ma to 200ma, v in = 2v, v out = 1.3v (note 4) l 3 0.1 0.5 na mv change in i set with v set change in v os with v set change in i set with v set change in v os with v set v set = 1.3v to 15v, v in = 20v, i load = 1ma v set = 1.3v to 15v, v in = 20v, i load = 1ma (note 4) v set = 0v to 1.3v, v in = 20v, i load = 1ma v set = 0v to 1.3v, v in = 20v, i load = 1ma (note 4) l l l l 30 0.03 150 0.3 400 0.6 600 2 na mv na mv dropout voltage i load = 1ma, 50ma l 220 270 300 mv mv i load = 150ma (note 5) 270 mv i load = 200ma (note 5) 350 mv gnd pin current v in = v out(nominal) (note 6) i load = 10a i load = 1ma i load = 50ma i load = 100ma i load = 200ma l l l l 1.9 2 3.2 4.5 7.6 3.5 5 7 13 ma ma ma ma ma output noise spectral density (notes 4, 8) i load = 200 ma, frequency = 10 hz, c out = 4.7 f , c set = 0.47 f , v out = 3.3 v i load = 200 ma, frequency = 10 hz, c out = 4.7 f , c set = 4.7 f , 1.3 v v out 15 v i load = 200 ma, frequency = 10 khz, c out = 4.7 f , c set = 0.47 f , 1.3 v v out 15 v i load = 200 ma, frequency = 10 khz, c out = 4.7 f , c set = 0.47 f , 0 v v out < 1.3 v 300 60 2 5 nv/ hz nv/ hz nv/ hz nv/ hz output rms noise (notes 4, 8) i load = 200 ma, bw = 10 hz to 100 khz, c out = 4.7 f , c set = 0.47 f , v out = 3.3 v i load = 200 ma, bw = 10 hz to 100 khz, c out = 4.7 f , c set = 4.7 f , 1.3 v v out 15 v i load = 200 ma, bw = 10 hz to 100 khz, c out = 4.7 f , c set = 4.7 f , 0 v v out < 1.3 v 1.9 0.8 1.6 v rms v rms v rms reference current rms output noise ( notes 4, 8) bw = 10hz to 100khz 6 na rms ripple rejection 1.3v v out 15v v in C v out = 2v (avg) (notes 4, 8) v ripple = 500 mv p-p , f ripple = 120 hz, i load = 200 ma, c out = 4.7 f , c set = 4.7 f v ripple = 150 mv p-p , f ripple = 10 khz, i load = 200 ma, c out = 4.7 f , c set = 0.47 f v ripple = 150 mv p-p , f ripple = 100 khz, i load = 200 ma, c out = 4.7 f , c set = 0.47 f v ripple = 150 mv p-p , f ripple = 1 mhz, i load = 200 ma, c out = 4.7 f , c set = 0.47 f v ripple = 80 mv p-p , f ripple = 10 mhz, i load = 200 ma, c out = 4.7 f , c set = 0.47 f 95 117 91 78 79 56 db db db db db ripple rejection 0v v out < 1.3v v in C v out = 2v (avg) (notes 4, 8) v ripple = 500 mv p-p , f ripple = 120 hz, i load = 200 ma, c out = 4.7 f , c set = 0.47 f v ripple = 50 mv p-p , f ripple = 10 khz, i load = 200 ma, c out = 4.7 f , c set = 0.47 f v ripple = 50 mv p-p , f ripple = 100 khz, i load = 200 ma, c out = 4.7 f , c set = 0.47 f v ripple = 50 mv p-p , f ripple = 1 mhz, i load = 200 ma, c out = 4.7 f , c set = 0.47 f v ripple = 50 mv p-p , f ripple = 10 mhz, i load = 200 ma, c out = 4.7 f , c set = 0.47 f 104 85 73 72 57 db db db db db en/uv pin threshold en/uv trip point rising (turn-on), v in = 2v l 1.18 1.24 1.32 v en/uv pin hysteresis en/uv trip point hysteresis, v in = 2v 170 mv en/uv pin current v en/uv = 0v, v in = 20v v en/uv = 1.24v, v in = 20v v en/uv = 20v, v in = 0v l l 0.2 8 1 15 a a a downloaded from: http:///
lt 3042 4 3042fa for more information www.linear.com/lt3042 electrical characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. parameter conditions min typ max units quiescent current in shutdown (v en/uv = 0v) v in = 6v l 0.3 1 10 a a internal current limit (note 12) v in = 2v, v out = 0v v in = 12v, v out = 0v v in = 20v, v out = 0v l l 220 130 270 300 180 320 250 ma ma ma programmable current limit programming scale factor: 2v< v in < 20v (note 11) v in = 2v, v out = 0v, r ilim = 625 v in = 2v, v out = 0v, r ilim = 2.5k l l 180 45 125 200 50 220 55 ma ? k ma ma pgfb trip point pgfb trip point rising l 291 300 309 mv pgfb hysteresis pgfb trip point hysteresis 7 mv pgfb pin current v in = 2v, v pgfb = 300mv 25 na pg output low voltage i pg = 100a l 30 100 mv pg leakage current v pg = 20v l 1 a reverse input current v in = C20v, v en/uv = 0v, v out = 0v, v set = 0v l 50 a reverse output current v in = 0, v out = 5v, set = open 2 5 a minimum load required (note 13) v out < 1v l 10 a thermal shutdown t j rising hysteresis 162 8 c c start-up time v out(nom) = 5v, i load = 200ma, c set = 0.47f, v in = 6v, v pgfb = 6v v out(nom) = 5v, i load = 200ma, c set = 4.7f, v in = 6v, v pgfb = 6v v out(nom) = 5v, i load = 200ma, c set = 4.7f, v in = 6v, r pg1 = 50k, r pg2 = 400k (with fast start-up to 90% of v out ) 55 550 10 ms ms ms thermal regulation 10ms pulse C0.01 %/w note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the en/uv pin threshold must be met to ensure device operation. note 3: maximum junction temperature limits operating conditions. the regulated output voltage specification does not apply for all possible combinations of input voltage and output current, especially due to the internal current limit foldback which starts to decrease current limit at v in C v out > 12 v. if operating at maximum output current, limit the input voltage range. if operating at the maximum input voltage, limit the output current range. note 4: outs ties directly to out. note 5: dropout voltage is the minimum input-to-output differential voltage needed to maintain regulation at a specified output current. the dropout voltage is measured when output is 1% out of regulation. this definition results in a higher dropout voltage compared to hard dropout which is measured when v in = v out(nominal) . for lower output voltages, below 1.5 v, dropout voltage is limited by the minimum input voltage specification. linear technology is unable to guarantee maximum dropout voltage specifications at high currents due to production test limitations with kelvin-sensing the package pins. please consult the typical performance characteristics for curves of dropout voltage as a function of output load current and temperature measured in a typical application circuit. note 6: gnd pin current is tested with v in = v out(nominal) and a current source load. therefore, the device is tested while operating in dropout. this is the worst-case gnd pin current. gnd pin current decreases at higher input voltages. note that gnd pin current does not include set pin or ilim pin current but quiescent current does include them. note 7: set and outs pins are clamped using diodes and two 25 series resistors. for less than 5 ms transients, this clamp circuitry can carry more than the rated current. refer to applications information for more information. note 8: adding a capacitor across the set pin resistor decreases output voltage noise. adding this capacitor bypasses the set pin resistors thermal noise as well as the reference currents noise. the output noise then equals the error amplifier noise. use of a set pin bypass capacitor also increases start-up time. note 9: the lt3042 is tested and specified under pulsed load conditions such that t j t a . the lt3042e is 100% tested at 25 c and performance is guaranteed from 0 c to 125 c. specifications over the C40 c to 125 c operating temperature range are assured by design, characterization, and correlation with statistical process controls. the lt3042i is guaranteed downloaded from: http:///
lt 3042 5 3042fa for more information www.linear.com/lt3042 typical performance characteristics offset voltage set pin current offset voltage (v out C v set ) set pin current set pin current offset voltage (v out C v set ) t j = 25c, unless otherwise noted. electrical characteristics over the full C40 c to 125 c operating temperature range. the lt3042mp is 100% tested and guaranteed over the full C55 c to 150 c operating temperature range. the lt3042h is 100% tested at the 150 c operating junction temperature. high junction temperatures degrade operating lifetimes. operating lifetime is derated at junction temperatures greater than 125 c. note 10: parasitic diodes exist internally between the ilim, pg, pgfb, set, outs, and out pins and the gnd pin. do not drive these pins more than 0.3v below the gnd pin during a fault condition. these pins must remain at a voltage more positive than gnd during normal operation. note 11: the current limit programming scale factor is specified while the internal backup current limit is not active. note that the internal current limit has foldback protection for v in C v out differentials greater than 12 v. note 12: the internal back-up current limit circuitry incorporates foldback protection that decreases current limit for v in C v out > 12 v. some level of output current is provided at all v in C v out differential voltages. consult the typical performance characteristics graph for current limit vs v in C v out . note 13: for output voltages less than 1 v, the lt3042 requires a 10 a minimum load current for stability. note 14: maximum out-to-outs differential is guaranteed by design. temperature (c) C75 set pin current (a) 101.0 99.2 100.8100.4 100.0 99.6 100.6100.2 99.899.4 99.0 25 125 C25 75 3042 g01 150 0 100 C50 50 v in = 2v i l = 1ma v out = 1.3v temperature (c) C75 offset voltage (mv) 2.0 1.50.5 C0.5C1.5 1.0 0 C1.0C2.0 25 125 C25 75 3042 g03 150 0 100 C50 50 v in = 2v i l = 1ma v out = 1.3v i set distribution (a) 98 101 99 3042 g02 102 100 n = 4354 v os distribution (mv) C2 1 C1 3042 g04 2 0 n = 4354 set pin current (a) 101.0 99.2 100.8100.4 100.0 99.6 100.6100.2 99.899.4 99.0 input voltage (v) 0 10 18 6 14 3042 g05 20 8 16 4 12 2 i l = 1ma v out = 1.3v 150c125c 25c C55c input voltage (v) 0 offset voltage (mv) 2.0 C1.5 1.50.5 C0.5 1.0 0 C1.0C2.0 10 18 6 14 3042 g06 20 8 16 4 12 2 i l = 1ma v out = 1.3v 150c125c 25c C55c downloaded from: http:///
lt 3042 6 3042fa for more information www.linear.com/lt3042 typical performance characteristics quiescent current typical dropout voltage dropout voltage quiescent current quiescent current in shutdown quiescent current t j = 25c, unless otherwise noted. set pin current offset voltage (v out C v set ) load regulation set pin current (a) 101.0 99.2 100.8100.4 100.0 99.6 100.6100.2 99.899.4 99.0 output voltage (v) 0 7.5 13.5 4.5 10.5 3042 g07 15 6 12 3 9 1.5 i l = 1ma v in = 20v 150c125c 25c C55c temperature (c) C75 quiescent current (ma) 3.0 2.51.5 0.5 2.01.0 0 25 125 C25 75 3042 g10 150 0 100 C50 50 v in = 2v v en/uv = v in i l = 10a r set = 13k output voltage (v) 0 quiescent current (ma) 3.5 2.52.0 3.01.5 0.5 1.0 0 10 6 14 3042 g13 16 8 4 12 2 v in = 20v v en/uv = v in i l = 10a 150c125c 25c C55c dropout voltage (mv) 500 50 450350 250 150 400300 200 100 0 output current (ma) 0 75 175 25 125 3042 g14 200 50 150 100 r set = 33.2k 150c125c 25c C55c dropout voltage (mv) 500 50 450350 250 150 400300 200 100 0 3042 g15 r set = 33.2k i l = 200ma i l = 150ma i l = 100ma i l = 1ma temperature (c) C75 25 125 C25 75 150 0 100 C50 50 20 2 1814 10 6 1612 84 0 temperature (c) C75 quiescent current (a) 25 125 C25 75 3042 g11 150 0 100 C50 50 v en/uv = 0v v in = 2v v in = 20v input voltage (v) 0 quiescent current (ma) 2.5 2.01.5 0.5 1.0 0 10 18 6 14 3042 g12 20 8 16 4 12 2 i l = 10a r set = 33.2k offset voltage (mv) 2.0 C1.5 1.50.5 0 C0.5 1.0 C1.0C2.0 output voltage (v) 0 7.5 13.5 4.5 10.5 3042 g08 15 6 12 3 9 1.5 i l = 1ma v in = 20v 150c125c 25c C55c temperature (c) C75 i set load regulation (na) 20 2 1814 10 6 1612 84 0 v os load regulation (mv) 0.20 0.02 0.180.14 0.10 0.06 0.160.12 0.08 0.04 0 25 125 C25 75 3042 g09 150 0 100 C50 50 v in = 2.5v ?i l = 1ma to 200ma v out = 1.3v v os i set downloaded from: http:///
lt 3042 7 3042fa for more information www.linear.com/lt3042 typical performance characteristics enable pin input current enable pin current negative enable pin current gnd pin current gnd pin current gnd pin current minimum input voltage en/uv turn-on threshold en/uv pin hysteresis t j = 25c, unless otherwise noted. gnd pin current (ma) 10 1 97 5 3 86 4 2 0 3042 g16 v in = 5v r set = 33.2k i l = 200ma i l = 150ma i l = 100ma i l = 1ma temperature (c) C75 25 125 C25 75 150 0 100 C50 50 temperature (c) C75 input uvlo threshold (v) 2.00 1.751.25 0.75 0.25 1.501.00 0.50 0 25 125 C25 75 3042 g19 150 0 100 C50 50 rising uvlo falling uvlo enable pin voltage (v) 0 en/uv pin current (a) 10 18 6 14 3042 g22 20 8 16 4 12 2 v in = 20v 5.0 0.5 4.53.5 2.5 1.5 4.03.0 2.0 1.0 0 150c125c 25c C55c enable pin voltage (v) 0 en/uv pin current (a) 10 18 6 14 3042 g23 20 8 16 4 12 2 v in = 20v v in = 2v 10 1 97 5 3 86 4 2 0 enable pin voltage (v) C20 en/uv pin current (a) C10 C2 C14 C6 3042 g24 0 C12 C4 C16 C8 C18 v in = 2v 0 C90 C10C30 C50 C70 C20C40 C60 C80 C100 150c125c 25c C55c temperature (c) C75 turn-on threshold (v) 1.32 1.301.26 1.22 1.281.24 1.20 1.18 25 125 C25 75 3042 g20 150 0 100 C50 50 v in = 2v v in = 10v temperature (c) C75 en/uv pin hysteresis (mv) 250 225175 125 200150 100 25 125 C25 75 3042 g21 150 0 100 C50 50 v in = 2v v in = 10v gnd pin current (ma) 8 1 75 3 64 2 0 output current (ma) 0 75 175 25 125 3042 g17 200 50 150 100 v in = 4.3v r set = 33.2k input voltage (v) 0 gnd pin current (ma) 8 76 5 4 3 2 1 0 5 9 3 7 3042 g18 10 4 8 2 6 1 r set = 33.2k r l = 16.5 r l = 3.3k r l = 33 r l = 66 r l = 330 downloaded from: http:///
lt 3042 8 3042fa for more information www.linear.com/lt3042 typical performance characteristics ilim pin current pgfb rising threshold pgfb hysteresis internal current limit programmable current limit programmable current limit t j = 25c, unless otherwise noted. input pin current internal current limit internal current limit enable pin voltage (v) C20 input current (ma) C10 C2 C14 C6 3042 g25 0 C12 C4 C16 C8 C18 v in = 2v 0.3 0.1 0.2 0 150c125c 25c C55c 0 10 18 6 14 20 8 16 4 12 2 current limit (ma) 500 50 450350 250 150 400300 200 100 0 3042 g28 r ilim = 0 150c125c 25c C55c input-to-output differential (v) start of foldback 0 100 180 60 140 200 80 160 40 120 20 ilim pin current (a) 500 50 450350 250 150 400300 200 100 0 3042 g31 v ilim = 0v r set = 33.2k output current (ma) v in = 2.5v v in = 5v v in = 10v current limit (ma) 500 50 450350 250 150 400300 200 100 0 3042 g26 r ilim = 0 v out = 0v v in = 7.5v v in = 2.5v temperature (c) C75 25 125 C25 75 150 0 100 C50 50 current limit (ma) 400 50 350250 150 300200 100 0 3042 g29 r ilim = 625 v out = 0v v in = 7.5v v in = 2.5v temperature (c) C75 25 125 C25 75 150 0 100 C50 50 pgfb rising threshold (mv) 310 292 308304 300 296 306302 298 294 290 3042 g32 v in = 2v temperature (c) C75 25 125 C25 75 150 0 100 C50 50 current limit (ma) 300 50 250150 200100 0 3042 g27 v in = 20v r ilim = 0 v out = 0v temperature (c) C75 25 125 C25 75 150 0 100 C50 50 current limit (ma) 100 10 9080 70 50 30 6040 20 0 3042 g30 r ilim = 2.49k v out = 0v v in = 7.5v v in = 2.5v temperature (c) C75 25 125 C25 75 150 0 100 C50 50 pgfb hysteresis (mv) 8 75 3 1 64 2 0 3042 g33 v in = 2v temperature (c) C75 25 125 C25 75 150 0 100 C50 50 downloaded from: http:///
lt 3042 9 3042fa for more information www.linear.com/lt3042 typical performance characteristics v out forced above v out(nominal) power supply ripple rejection power supply ripple rejection pg output low voltage pg pin leakage current i set during start-up with fast start-up enabled i set during start-up with fast start-up enabled output overshoot recovery current sink output overshoot recovery current sink t j = 25c, unless otherwise noted. v pg (mv) 50 5 4535 25 15 4030 20 10 0 3042 g34 v in = 2v v pgfb = 290mv i pg = 100a temperature (c) C75 25 125 C25 75 150 0 100 C50 50 0 10 18 6 14 20 8 16 4 12 2 i set (ma) 3.0 2.51.5 0.5 2.01.0 0 3042 g37 v in -to-v set differential (v) v pgfb = 290mv v set = 1.3v current (ma) 14 2 10 6 12 84 0 3042 g40 output voltage (v) 4 10 14 8 12 15 9 13 7 5 6 11 v in = 5v r set = 33.2k output current input current v out C v set (mv) 0 output sink current (ma) 10 86 2 40 5 15 3042 g38 20 10 v in = 5v r set = 33.2k 155c130c 25c C55c psrr (db) 120 110 70 8050 30 100 9060 40 20 3042 g41 frequency (hz) 10 100 1k 1m 10m 100k 10k v in = 5v r set = 33.2k c out = 4.7f i l = 200ma c set = 4.7f c set = 0.47f output sink current (ma) 7 1 53 64 2 0 3042 g39 temperature (c) C75 25 125 C25 75 150 0 100 C50 50 v in = 5v r set = 33.2k v out C v set > 5mv psrr (db) 120 110 70 8050 30 100 9060 40 20 3042 g42 frequency (hz) 10 100 1k 1m 10m 100k 10k v in = 5v r set = 33.2k c set = 0.47f i l = 200ma c out = 4.7f c out = 22f i pg (na) 100 10 9070 50 30 8060 40 20 0 3042 g35 v pg = 2v v pgfb = 310mv temperature (c) C75 25 125 C25 75 150 0 100 C50 50 i set (ma) 2.5 2.01.0 1.50.5 0 3042 g36 temperature (c) C75 25 125 C25 75 150 0 100 C50 50 v in = 2.5v v pgfb = 290mv v set = 1.3v downloaded from: http:///
lt 3042 10 3042fa for more information www.linear.com/lt3042 typical performance characteristics integrated rms output noise (10hz to 100khz) noise spectral density integrated rms output noise (10hz to 100khz) noise spectral density integrated rms output noise (10hz to 100khz) noise spectral density t j = 25c, unless otherwise noted. power supply ripple rejection power supply ripple rejection as a function of error amplifier input pair power supply ripple rejection psrr (db) 120 110 70 8050 30 100 9060 40 20 3042 g43 frequency (hz) 10 100 1k 1m 10m 100k 10k v in = 5v r set = 33.2k c out = 4.7f c set = 0.47f i l = 200ma i l = 100ma i l = 50ma i l = 1ma 0 100 180 60 140 200 80 160 40 120 20 rms output noise ( v rms ) 2.0 0.2 1.81.4 1.0 0.6 1.61.2 0.8 0.4 0 3042 g46 load current (ma) v in = 5v r set = 33.2k c out = 4.7f c set = 4.7f output noise (nv / hz ) 100 1 10 0.1 3042 g49 frequency (hz) 10 100 1k 1m 10m 100k 10k v in = 5v r set = 33.2k c set = 4.7f i l = 200ma c out = 4.7f c out = 22f psrr (db) 120 110 70 8050 30 100 9060 40 20 3042 g44 frequency (hz) 10 100 1k 1m 10m 100k 10k v in = v out + 2v i l = 200ma c out = 4.7f c set = 0.47f v out 1.3v 0.6v < v out < 1.3v v out 0.6v 10 100 1 0.1 0.01 rms output noise (v rms ) 9 86 4 2 75 3 1 0 3042 g47 set pin capacitance (f) v in = 5v r set = 33.2k c out = 4.7f i l = 200ma output noise (nv / hz ) 100 1 10 0.1 3042 g50 frequency (hz) 10 100 1k 1m 10m 100k 10k v in = 5v r set = 33.2k c set = 4.7f c out = 4.7f i l = 200ma i l = 100ma i l = 50ma i l = 1ma input-to-output differential (v) psrr (db) 100 70 8050 30 9060 40 0 10 20 3042 g45 0 1 2 5 4 3 i l = 200ma r set = 33.2k c out = 4.7f c set = 0.47f 100khz500khz 1mhz 2mhz rms output noise (v rms ) 2.00.2 1.81.4 1.0 0.6 1.61.2 0.8 0.4 0 output voltage (v) 0 7.5 13.5 4.5 10.5 3042 g57 15 6 12 3 9 1.5 v in = v out + 2v c set = 4.7f c out = 4.7f i load = 200ma output noise (nv / hz ) 1000 1 100 10 0.1 3042 g48 frequency (hz) 10 100 1k 1m 10m 100k 10k v in = 5v r set = 33.2k c out = 4.7f i l = 200ma c set = 0.047f c set = 0.47f c set = 1f c set = 4.7f c set = 22f downloaded from: http:///
lt 3042 11 3042fa for more information www.linear.com/lt3042 noise spectral density as a function of error amplifier input pair output noise (nv / hz ) 1000 1 100 10 0.1 3042 g51 frequency (hz) 10 100 1k 1m 10m 100k 10k v in = v out + 2v i l = 200ma c out = 4.7f c set = 4.7f v out 1.3v 0.6v < v out < 1.3v v out 0.6v typical performance characteristics start-up time with and without fast start-up circuitry for large c set input supply ramp-up and ramp-down output noise: 10hz to 100khz load transient response line transient response t j = 25c, unless otherwise noted. 5v/div 1ms/div 3042 g52 v in = 5v r set = 33.2k c out = 4.7f c set = 4.7f i l = 200ma 200ma/div 10mv/div 20s/div 3042 g53 v in = 5v r set = 33.2k c out = 4.7f c set = 0.47f load step = 10ma to 200ma load step output voltage 500mv/div 1mv/div 5s/div 3042 g54 v in = 4v to 4.5v r set = 33.2k c out = 4.7f c set = 0.47f i l = 200ma output voltage input voltage 500mv/div 2mv/div 100ms/div 3042 g55 v in = 5v r set = 33.2k c out = 4.7f c set = 4.7f r l = 16.5 pulse en/uv output with fast start-up (set at 95%) output without fast start-up 2v/div 50ms/div 3042 g56 v in = 0v to 5v r set = 33.2k c out = 4.7f c set = 0.47f r l = 16.5 output voltage input voltage downloaded from: http:///
lt 3042 12 3042fa for more information www.linear.com/lt3042 pin functions in ( pins 1, 2): input. these pins supply power to the regulator. the lt3042 requires a bypass capacitor at the in pin. in general, a batterys output impedance rises with frequency, so include a bypass capacitor in battery - powered applications. while a 4.7 f input bypass capacitor gener- ally suffices, applications with large load transients may require higher input capacitance to prevent input supply droop. the lt 3042 withstands reverse voltages on in with respect to gnd, outs and out. in the case of a reversed input, which occurs if a battery is plugged-in backwards, the lt3042 acts as if a diode is in series with its input. hence, no reverse current flows into the lt3042 and no negative voltage appears at the load. the device protects itself and the load.en/ uv ( pin 3): enable/uvlo. pulling the lt3042s en/uv pin low places the part in shutdown. quiescent current in shutdown drops to less than 1 a and the output voltage turns off. alternatively, the en/uv pin can set an input supply undervoltage lockout ( uvlo) threshold using a resistor divider between in, en/uv and gnd. the lt3042 typically turns on when the en/uv voltage exceeds 1.24 v on its rising edge, with a 170 mv hysteresis on its falling edge. the en/uv pin can be driven above the input voltage and maintain proper functionality. if unused, tie en/uv to in. do not float the en/uv pin.pg ( pin 4): power good. pg is an open-collector flag that indicates output voltage regulation. pg pulls low if pgfb is below 300 mv. if the power good functionality is not needed, float the pg pin. a parasitic substrate diode exists between pg and gnd pins of the lt3042; do not drive pg more than 0.3 v below gnd during normal operation or during a fault condition.ilim ( pin 5): current limit programming pin. connecting a resistor between ilim and gnd programs the current limit. for best accuracy, kelvin connect this resistor directly to the lt3042s gnd pin. the programming scale factor is nominally 125 ma?k. the ilim pin sources current proportional (1:400) to output current; therefore, it also serves as a current monitoring pin with a 0 v to 300 mv range. if the programmable current limit functionality is not needed, tie ilim to gnd. a parasitic substrate diode exists between ilim and gnd pins of the lt3042; do not drive ilim more than 0.3 v below gnd during normal operation or during a fault condition.pgfb ( pin 6): power good feedback. the pg pin pulls high if pgfb increases beyond 300 mv on its rising edge, with 7 mv hysteresis on its falling edge. connecting an external resistor divider between out, pgfb and gnd sets the programmable power good threshold with the following transfer function : 0.3 v ? (1 + r pg2 /r pg1 ). as discussed in the applications information section, pgfb also activates the fast start-up circuitry. if power good and fast start-up functionalities are not needed, tie pgfb to in. if reverse input protection is required, tie the anode of a 1n4148 diode to v in and the cathode to pgfb. a parasitic substrate diode exists between pgfb and gnd pins of the lt3042; do not drive pgfb more than 0.3 v below gnd during normal operation or during a fault condition.set ( pin 7): set. this pin is the inverting input of the error amplifier and the regulation set-point for the lt3042. set sources a precision 100 a current that flows through an external resistor connected between set and gnd. the lt3042 s output voltage is determined by v set = i set ?? r set . output voltage range is from zero to 15 v. adding a capaci- tor from set to gnd improves noise, psrr and transient response at the expense of increased start-up time. for optimum load regulation, kelvin connect the ground side of the set pin resistor directly to the load. a parasitic substrate diode exists between set and gnd pins of the lt3042; do not drive set more than 0.3 v below gnd during normal operation or during a fault condition.gnd ( pin 8, exposed pad pin 11): ground. the exposed backside is an electrical connection to gnd. to ensure proper electrical and thermal performance, solder the exposed backside to the pcb ground and tie it directly to the gnd pin. downloaded from: http:///
lt 3042 13 3042fa for more information www.linear.com/lt3042 pin functions block diagram v +C output overshoot recovery erroramplifier internal currentlimit programmable current limit qc qp out c out c in v in r l v out 1.5v 100a 2ma v +C 300mv 270 qpwr +C driver +C C+ v +C 300mv ilim r ilim C+ 10 in1, 2 thermal shdn current reference fast start-up input uvlo set-to-outs protection clamp input uvlocurrent limit thermal shdn dropout r set r pg r pg2 r pg1 c set +C fast start-up disable logic 5 outs 3042 bd 9 set 7 pg 4 pgfb 6 en/uv 3 gnd 8 v +C 300mv v +C 1.24v programmablepower good +C enable comparator bias outs ( pin 9): output sense. this pin is the noninvert- ing input to the error amplifier. for optimal transient performance and load regulation, kelvin connect outs directly to the output capacitor and the load. also, tie the gnd connections of the output capacitor and the set pin capacitor directly together. moreover, place the input and output capacitors ( and their gnd connections) very close together. a parasitic substrate diode exists between outs and gnd pins of the lt3042; do not drive outs more than 0.3 v below gnd during normal operation or during a fault condition. out ( pin 10): output. this pin supplies power to the load. for stability, use a minimum 4.7 f output capacitor with an esr below 50 m and an esl below 2 nh. large load transients require larger output capacitance to limit peak voltage transients. refer to the applications information section for more information on output capacitance. a parasitic substrate diode exists between out and gnd pins of the lt3042; do not drive out more than 0.3 v below gnd during normal operation or during a fault condition. downloaded from: http:///
lt 3042 14 3042fa for more information www.linear.com/lt3042 applications information the lt3042 is a high performance low dropout linear regulator featuring lt c s ultralow noise (2 nv/ hz at 10khz) and ultrahigh psrr (79 db at 1 mhz) architecture for powering noise sensitive applications. designed as a precision current source followed by a high performance rail-to-rail voltage buffer, the lt3042 can be easily paral- leled to further reduce noise, increase output current and spread heat on the pcb. the device additionally features programmable current limit, fast start-up capability and programmable power good. the lt3042 is easy to use and incorporates all of the protection features expected in high performance regula- tors. included are short-circuit protection, safe operating area protection, reverse battery protection, reverse current protection, and thermal shutdown with hysteresis. output voltage the lt3042 incorporates a precision 100 a current source flowing out of the set pin, which also ties to the error amplifier s inverting input. figure 1 illustrates that connect - ing a resistor from set to ground generates a reference voltage for the error amplifier. this reference voltage is simply the product of the set pin current and the set pin resistor. the error amplifiers unity-gain configuration produces a low impedance version of this voltage on its noninverting input, i.e. the outs pin, which is externally tied to the out pin. the lt3042s rail-to-rail error amplifier and current refer- ence allows for a wide output voltage range from 0 v ( us- ing a 0 resistor) to v in minus dropout up to 15 v. a pnp-based input pair is active for 0 v to 0.6 v output and an npn-based input pair is active for output voltages greater than 1.3 v, with a smooth transition between the two input pairs from 0.6 v to 1.3 v output. while the npn-based input pair is designed to offer the best overall performance, refer to the electrical characteristics table for details on offset voltage, set pin current, output noise and psrr variation with the error amp input pair. table 1 lists many common output voltages and their corresponding 1% r set resistors . table 1. 1% resistor for common output voltages v out (v) r set (k) 2.5 24.9 3.3 33.2 5 49.9 12 121 15 150 the benefit of using a current reference compared with a voltage reference as used in conventional regulators is that the regulator always operates in unity gain configura- tion, independent of the programmed output voltage. this allows the lt3042 to have loop gain, frequency response and bandwidth independent of the output voltage. as a result, noise, psrr and transient performance do not change with output voltage. moreover, since none of the error amp gain is needed to amplify the set pin voltage to a higher output voltage, output load regulation is more tightly specified in the hundreds of microvolts range and not as a fixed percentage of the output voltage. since the zero tc current source is highly accurate, the set pin resistor can become the limiting factor in achieving high accuracy. hence, it should be a precision resistor. additionally, any leakage paths to or from the set pin create errors in the output voltage. if necessary, use high quality insulation ( e.g., teflon, kel-f); moreover, clean- ing of all insulating surfaces to remove fluxes and other residues may be required. high humidity environments may require a surface coating at the set pin to provide a moisture barrier. minimize board leakage by encircling the set pin with a guard ring operated at a potential close to itself ideally tied to the out pin. guarding both sides of the circuit board is recommended. bulk leakage reduction depends +C 100a in en/uvpgfb gnd out lt3042 ilim pg 4.7f 4.7f v in 5v 5% 0.47f v out, 3.3v i out(max) , 200ma 3042 f01 33.2k set outs figure 1. basic adjustable regulator downloaded from: http:///
lt 3042 15 3042fa for more information www.linear.com/lt3042 applications information on the guard ring width. leakages of 100 na into or out of the set pin creates a 0.1% error in the reference voltage. leakages of this magnitude, coupled with other sources of leakage, can cause significant errors in the output voltage, especially over wide operating temperature range. figure ?2 illustrates a typical guard ring layout technique. stability and output capacitancethe lt3042 requires an output capacitor for stability . given its high bandwidth ( about 1 mhz), lt c recommends low esr and esl ceramic capacitors. a minimum 4.7 f output capacitor with an esr below 50 m and an esl below 2nh is required for stability. to minimize effects of board inductances on the lt3042 s dynamic performance, kelvin connect the outs pin directly to the output capacitor as well as kelvin connect the gnd side of the set pin capaci- tor ( c set ) directly to the gnd side of the output capacitor. also, tie the input capacitors gnd connection as close as possible to the output capacitors gnd connection. given the high psrr and low noise performance attained using a single 4.7 f ceramic output capacitor, larger values of output capacitor only marginally improves the perfor- mance because the regulator bandwidth decreases with increasing output capacitance hence, there is little to be gained by using larger than the minimum 4.7 f output capacitor. nonetheless, larger values of output capacitance do decrease peak output deviations during a load transient . note that bypass capacitors used to decouple individual components powered by the lt3042 increase the effective output capacitance. give extra consideration to the type of ceramic capacitors used. they are manufactured with a variety of dielectrics, each with different behavior across temperature and applied voltage. the most common dielectrics used are specified with eia temperature characteristic codes of z5u, y5v, 3042 f02 11 out set 10 96 7 8 45 3 2 1 figure 2. guard ring layout figure 3. c out and c set connections for stability +C 100a in en/uvpgfb gnd out lt3042 ilim pg c out c in v in v out i out(max) 200ma 3042 f01 r set set outs c set since the set pin is a high impedance node, unwanted signals may couple into the set pin and cause erratic behavior. this is most noticeable when operating with a minimum output capacitor at heavy load currents. by- passing the set pin with a small capacitance to ground resolves this issue 10nf is sufficient. for applications requiring higher accuracy or an adjust- able output voltage, the set pin may be actively driven by an external voltage source capable of sinking 100 a. connecting a precision voltage reference to the set pin eliminates any errors present in the output voltage due to the reference current and set pin resistor tolerances.output sensing the lt3042 s outs pin provides a kelvin sense connection to the output. the set pin resistors gnd side provides a kelvin sense connection to the loads gnd side. additionally, as shown in figure 3, it is very important for stability to tie the outs pin directly to the output capaci- tor ( c out ) and the gnd side of set pin capacitor ( c set ) directly to the gnd side of c out as well as keep the gnd sides of input capacitor ( c in ) and c out close together. refer to the pcb layout considerations section for an example layout that meets these requirements. downloaded from: http:///
lt 3042 16 3042fa for more information www.linear.com/lt3042 applications information x5r and x7r. the z5u and y5v dielectrics are good for providing high capacitance in the small packages, but they tend to have stronger voltage and temperature coefficients as shown in figures 4 and 5. when used with a 5 v regu- lator, a 16 v 10 f y5v capacitor can exhibit an effective value as low as 1 f to 2 f for the dc bias voltage applied over the operating temperature range. x5r and x7r dielectrics result in more stable character- istics and are thus more suitable for lt3042. the x7r dielectric has better stability across temperature, while the x5r is less expensive and is available in higher values. nonetheless, care must still be exercised when using x5r and x7r capacitors. the x5r and x7 r codes only specify operating temperature range and the maximum capacitance change over temperature. while capacitance change due to dc bias for x5r and x7r is better than y5v and z5u dielectrics, it can still be significant enough to drop capacitance below sufficient levels. as shown in figure 6, capacitor dc bias characteristics tend to improve as component case size increases, but verification of expected capacitance at the operating voltage is highly recommended. voltage and temperature coefficients are not the only sources of problems. some ceramic capacitors have a piezoelectric response. a piezoelectric device generates voltage across its terminals due to mechanical stress upon it, similar to how a piezoelectric microphone works. for a ceramic capacitor, this stress can be induced by mechanical vibrations within the system or due to thermal transients. stability and input capacitance the lt3042 is stable with a minimum 4.7 f in pin ca- pacitor. lt c recommends using low esr ceramic ca- pacitors. in cases where long wires connect the power supply to the lt3042s input and ground terminals, the use of low value input capacitors combined with a large load current can result in instability. the resonant lc tank circuit formed by the wire inductance and the input capaci- tor is the cause and not because of lt3042s instability. the self-inductance, or isolated inductance, of a wire is directly proportional to its length. the wire diameter, figure 4. ceramic capacitor dc bias characteristics figure 5. ceramic capacitor temperature characteristics figure 6. capacitor voltage coefficient for different case sizes dc bias voltage (v) both capacitors are 16v, 1210 case size, 10f 0 C100 change in value (%) C80 6 4 2 8 10 12 3042 f04 14 0 20 C60 C40 x5r y5v C20 16 temperature (c) C50 C100 change in value (%) C80 25 0 C25 50 75 100 3042 f05 0 20 40 C60 C40 y5v C20 125 both capacitors are 16v, 1210 case size, 10f x5r dc bias (v) 1 C100 change in value (%) C80 C60 C40 C20 0 20 5 10 15 20 3042 f06 25 1210, 2.2mm thick1206, 1.8mm thick 0805, 1.4mm thick murata: x7r, 25v,4.7f ceramic downloaded from: http:///
lt 3042 17 3042fa for more information www.linear.com/lt3042 applications information however, has less influence on its self-inductance. for example, the self-inductance of a 2- awg isolated wire with a diameter of 0.26" is about half the inductance of a 30- awg wire with a diameter of 0.01". one foot of 30- awg wire has 465nh of self-inductance. several methods exist to reduce a wires self-inductance. one method divides the current flowing towards the lt3042 between two parallel conductors. in this case, placing the wires further apart reduces the inductance; up to a 50% reduction when placed only a few inches apart. splitting the wires connect two equal inductors in parallel. however , when placed in close proximity to each other, their mu- tual inductance adds to the overall self inductance of the wires therefore a 50% reduction is not possible in such cases. the second and more effective technique to reduce the overall inductance is to place the forward and return current conductors ( the input and ground wires) in close proximity. tw o 30- awg wires separated by 0.02" reduce the overall inductance to about one-fifth of a single wire. if a battery mounted in close proximity powers the lt3042 , a 4.7 f input capacitor suffices for stability. however, if a distantly located supply powers the lt3042, use a larger value input capacitor. use a rough guideline of 1 f ( in addition to the 4.7 f minimum) per 8" of wire length. the minimum input capacitance needed to stabilize the application also varies with the output capacitance as well as the load current. placing additional capacitance on the lt3042 s output helps. however, this requires significantly more capacitance compared to additional input bypassing . series resistance between the supply and the lt3042 input also helps stabilize the application; as little as 0.1 to 0.5 suffices. this impedance dampens the lc tank circuit at the expense of dropout voltage. a better alternative is to use a higher esr tantalum or electrolytic capacitor at the lt3042 input in parallel with a 4.7f ceramic capacitor. output noise the lt3042 offers many advantages with respect to noise performance. traditional linear regulators have several sources of noise. the most critical noise sources for a tra- ditional regulator are its voltage reference, error amplifier, noise from the resistor divider network used for setting output voltage and the noise gain created by this resistor divider. many low noise regulators pin out their voltage reference to allow for noise reduction by bypassing the reference voltage. unlike most linear regulators, the lt3042 does not use a voltage reference; instead, it uses a 100 a current refer- ence. the current reference operates with typical noise current level of 20 pa/ hz (6 na rms over a 10 hz to 100 khz bandwidth). the resultant voltage noise equals the current noise multiplied by the resistor value, which in turn is rms summed with the error amplifier s noise and the resistor s own noise of 4 ktr whereby k = boltzmann s constant 1.38 ? 10 C23 j/k and t is the absolute temperature. one problem that conventional linear regulators face is that the resistor divider setting the output voltage gains up the reference noise. in contrast, the lt3042s unity-gain follower architecture presents no gain from the set pin to the output. therefore, if a capacitor bypasses the set pin resistor, then the output noise is independent of the programmed output voltage. the resultant output noise is then set just by the error amplifiers noise typically 2nv/ hz from 10 khz to 1 mhz and 0.8 v rms in a 10 hz to 100 khz bandwidth using a 4.7 f set pin capacitor. paralleling multiple lt3042s further reduces noise by n , for n parallel regulators. refer to the typical performance characteristics section for noise spectral density and rms integrated noise over various load currents and set pin capacitances. set pin (bypass) capacitance: noise, psrr, transient response and soft-start in addition to reducing output noise, using a set pin bypass capacitor also improves psrr and transient performance. note that any bypass capacitor leakage deteriorates the lt3042s dc regulation. capacitor leakage of even 100 na is a 0.1% dc error . therefore, lt c recommends the use of a good quality low leakage ceramic capacitor. using a set pin bypass capacitor also soft - starts the output and limits inrush current . the rc time constant, formed by the set pin resistor and capacitor, controls soft-start time. ramp-up rate from 0 to 90% of nominal v out is: t ss 2.3 ? r set ? c set downloaded from: http:///
lt 3042 18 3042fa for more information www.linear.com/lt3042 applications information fast start-upfor ultralow noise applications that require low 1/f noise (i.e. at frequencies below 100 hz), a larger value set pin capacitor is required, up to 22 f . while normally this would significantly increase the regulators start-up time, the lt3042 incorporates fast start-up circuitry that increases the set pin current to about 2ma during start-up. as shown in the block diagram, the 2 ma current source remains engaged while pgfb is below 300 mv, unless the regulator is in current limit, dropout, thermal shutdown or input voltage is below minimum v in . if fast start-up capability is not used, tie pgfb to in or to out for output voltages above 300 mv. note that doing so also disables power good functionality.filtering high frequency spikes for applications where the lt3042 is used to post - regulate a switching converter, its high psrr effectively sup- presses any noise present at the switchers switching frequency typically 100 khz to 4 mhz. however, the very high frequency (100 s of mhz ) spikes beyond the lt3042s bandwidth associated with the switchers power switch transition times will almost directly pass through the lt3042. while the output capacitor is partly intended to absorb these spikes, its esl will limit its ability at these frequencies. a ferrite bead or even the inductance associated with a short ( e.g . 0.5 ") pcb trace between the switchers output and the lt3042s input can serve as an lc-filter to suppress these very high frequency spikes. enable/uvlo the en/uv pin is used to put the regulator into a mi- cropower shutdown state. the lt3042 has an accurate 1.24v turn-on threshold on the en/uv pin with 170 mv of hysteresis. this threshold can be used in conjunction with a resistor divider from the input supply to define an accurate undervoltage lockout ( uvlo) threshold for the regulator. the en / uv pin current ( i en ) at the threshold from the electrical characteristics table needs to be considered when calculating the resistor divider network: v in(uvlo) = 1.24v ? 1 + r en2 r en1 ?? ? ?? ? + i en ?r en2 the en/uv pin current ( i en ) can be ignored if r en1 is less than 100k. if unused, tie en/uv pin to in.programmable power good as illustrated in the block diagram, power good thresh- old is user programmable using the ratio of two external resistors, r pg2 and r pg1 : v out(pg _ threshold) = 0.3v ? 1 + r pg2 r pg1 ?? ? ?? ? + i pgfb ?r pg2 if the pgfb pin increases above 300 mv, the open - collector pg pin de-asserts and becomes high impedance. the power good comparator has 7 mv hysteresis and 5 s of deglitching. the pgfb pin current ( i pgfb ) from the electrical characteristics table must be considered when determining the resistor divider network. the pgfb pin current ( i pgfb ) can be ignored if r pg1 is less than 30 k. if power good functionality is not used, float the pg pin. please note that programmable power good and fast start-up capabilities are disabled for output voltages below 300mv. externally programmable current limit the ilim pins current limit threshold is 300 mv. con- necting a resistor from ilim to gnd sets the maximum current flowing out of the ilim pin, which in turn programs the lt3042s current limit. the programming scale factor is 125 ma?k. for example, a 1 k resistor programs the current limit to 125 ma and a 2 k resistor programs the current limit to 62.5 ma. for good accuracy, kelvin connect this resistor to the lt3042s gnd pin. in cases where in-to-out differential is greater than 12 v, the lt3042s foldback circuitry decreases the internal current limit. as a result, internal current limit may over- ride the externally programmed current limit level to keep the lt3042 within its safe-operating-area ( soa). see the internal current limit vs input - to - output differential graph in the typical performance characteristics section. as shown in the block diagram, the ilim pin sources current proportional (1:400) to output current; therefore, it also serves as a current monitoring pin with a 0 v to 300 mv range . if external current limit or current monitoring is not used, tie ilim to gnd. downloaded from: http:///
lt 3042 19 3042fa for more information www.linear.com/lt3042 applications information output overshoot recovery during a load step from full load to no load ( or light load), the output voltage overshoots before the regulator responds to turn the power transistor off. given that there is no load ( or very light load) present at the output, it takes a long time to discharge the output capacitor. as illustrated in the block diagram, the lt3042 incorporates an overshoot recovery circuitry that turns on a current sink to discharge the output capacitor in the event outs is higher than set. this current is typically about 4 ma. no load recovery is disabled for input voltages less than 2.5v or output voltages less than 1.5v. if outs is externally held above set, the current sink turns on in an attempt to restore outs to its programmed voltage. the current sink remains on until the external circuitry releases outs. direct paralleling for higher current higher output current is obtained by paralleling multiple lt3042s. tie all set pins together and all in pins together. connect the out pins together using small pieces of pcb trace ( used as a ballast resistor) to equalize currents in the lt3042s. pcb trace resistance in milliohms/inch is shown in table 2. table 2. pc board trace resistance weight (oz) 10mil width 20mil width 1 54.3 27.1 2 27.1 13.6 trace resistance is measured in m/in. the small worst - case offset of 2 mv for each paralleled lt3042 minimizes the required ballast resistor value. figure 7 illustrates that two lt3042 s , each using a 50 m pcb trace ballast resistor, provide better than 20% accurate output current sharing at full load. the two 50 m external resis - tors only add 10 mv of output regulation drop with a 400 ma maximum current. with a 3.3 v output, this only adds 0.3% to the regulation accuracy. as has been discussed previously , tie the outs pin directly to the output capacitor . more than two lt3042s can also be paralleled for even higher output current and lower output noise. paralleling multiple lt3042s is also useful for distributing heat on the pcb. for applications with high input-to-output voltage differential, an input series resistor or resistor in parallel with the lt3042 can also be used to spread heat. pcb layout considerations given the lt3042s high bandwidth and ultrahigh psrr, careful pcb layout must be employed to achieve full device performance. figure 8 shows an example layout that delivers full performance of the regulator. refer to the lt3042 s dc2246 a demo board manual for further details . thermal considerationsthe lt3042 has internal power and thermal limiting circuits that protect the device under overload conditions. the thermal shutdown temperature is nominally 162 c with about 8 c of hysteresis. for continuous normal load condi - tions, do not exceed the maximum junction temperature, (125c for e-, i-grades and 150 c for h-, mp-grades). it is important to consider all sources of thermal resistance from junction to ambient. this includes junction-to-case, case-to-heat sink interface, heat sink resistance or circuit board-to-ambient as the application dictates. additionally, +C 100a in en/uvpgfb gnd out lt3042 ilim pg 4.7f 50m v out 3.3vi out(max) 400ma 3042 f07 16.5k set outs +C 100a in en/uvpgfb gnd out lt3042 ilim pg 4.7f 50m 10f v in 5v 5% set outs 0.47f figure 7. parallel devices downloaded from: http:///
lt 3042 20 3042fa for more information www.linear.com/lt3042 applications information achieving low thermal resistance necessitates attention to detail and careful pcb layout. table 3. measured thermal resistance for dfn package copper area board area thermal resistance top side* bottom side 2500mm 2 2500mm 2 2500mm 2 34c/w 1000mm 2 2500mm 2 2500mm 2 34c/w 225mm 2 2500mm 2 2500mm 2 35c/w 100mm 2 2500mm 2 2500mm 2 36c/w *device is mounted on topside table 4. measured thermal resistance for msop package copper area board area thermal resistance top side* bottom side 2500mm 2 2500mm 2 2500mm 2 33c/w 1000 mm 2 2500mm 2 2500mm 2 33c/w 225mm 2 2500mm 2 2500mm 2 34c/w 100mm 2 2500mm 2 2500mm 2 35c/w *device is mounted on topside calculating junction temperature example: given an output voltage of 2.5 v and input voltage of 5 v 5%, output current range from 1 ma to 200 ma, and a maximum ambient temperature of 85 c, what is the maximum junction temperature?the lt3042s power dissipation is: i out(max) ? (v in(max) C v out ) + i gnd ? v in(max) where: i out(max) = 200ma v in(max) = 5.25v i gnd (at i out = 200ma and v in = 5.25v) = 7.2ma thus: p diss = 0.2 a ? (5.25 v C 2.5 v ) + 7.2 ma ? 5.25 v = 0.59 w using a dfn package, the thermal resistance is in the range of 34 c/w to 36 c/w depending on the copper area. therefore, the junction temperature rise above ambient approximately equals: 0.59 w ? 35c/w = 20.7c 3042 f08 in out set gnd figure 8. example dfn layout consider all heat sources in close proximity to the lt3042. the undersides of the dfn and msop packages have exposed metal from the lead frame to the die attachment. both packages allow heat to directly transfer from the die junction to the pcb metal to limit maximum operating junction temperature. the dual-in-line pin arrangement allows metal to extend beyond the ends of the package on the topside (component side) of the pcb. for surface mount devices, heat sinking is accomplished by using the heat spreading capabilities of the pcb and its copper traces. copper board stiffeners and plated through - holes can also be used to spread the heat generated by the regulator. tables 3 and 4 list thermal resistance as a function of copper area on a fixed board size. all measurements were taken in still air on a 4 layer fr-4 board with 1 oz solid internal planes and 2 oz top/bottom planes with a total board thick- ness of 1.6 mm. the four layers were electrically isolated with no thermal vias present. pcb layers, copper weight, board layout and thermal vias affect the resultant thermal resistance. for more information on thermal resistance and high thermal conductivity test boards, refer to jedec standard jesd51, notably jesd51-7 and jesd51-12. downloaded from: http:///
lt 3042 21 3042fa for more information www.linear.com/lt3042 the maximum junction temperature equals the maxi- mum ambient temperature plus the maximum junction temperature rise above ambient: t jmax = 85c + 20.7c = 105.7c overload recovery like many ic power regulators, the lt3042 incorporates safe-operating-area ( soa) protection. the soa protection activates at input-to-output differential voltages greater than 12 v. the soa protection decreases the current limit as the input-to-output differential increases and keeps the power transistor inside a safe operating region for all values of input-to-output voltages up to the lt3042s absolute maximum ratings. the lt3042 provides some level of output current for all values of input-to-output dif- ferentials. refer to the current limit curves in the typical performance characteristics section. when power is first applied and input voltage rises, the output follows the input and keeps the input-to-output differential low to allow the regulator to supply large output current and start-up into high current loads. due to current limit foldback, however, at high input volt- ages a problem can occur if the output voltage is low and the load current is high. such situations occur after the removal of a short-circuit or if the en/uv pin is pulled high after the input voltage has already turned on. the load line in such cases intersects the output current profile at two points. the regulator now has two stable operating points. with this double intersection, the input power supply may need to be cycled down to zero and brought back up again to make the output recover. other linear regulators with foldback current limit protection ( such as the lt1965 and lt1963a, etc.) also exhibit this phenomenon, so it is not unique to the lt3042. protection features the lt3042 incorporates several protection features for battery-powered applications. precision current limit and thermal overload protection protect the lt3042 against overload and fault conditions at the devices output. for normal operation, do not allow the junction temperature to exceed 125c (e-, i-grade) or 150c (h-, mp-grade).to protect the lt3042s low noise error amplifier, the set- to-outs protection clamp limits the maximum volt- age between set and outs to 15 v with a maximum dc current of 20 ma through the clamp. so for applications where set is actively driven by a voltage source, the voltage source must be current limited to 20 ma or less. moreover, to limit the transient current flowing through these clamps during a transient fault condition, limit the maximum value of the set pin capacitor (c set ) to 22f. the lt3042 also incorporates reverse input protection whereby the in pin withstands reverse voltages of up to C20v without causing any input current flow and without developing negative voltages at the out pin. the regulator protects both itself and the load against batteries that are plugged-in backwards. in circuits where a backup battery is required, several different input/output conditions can occur. the output voltage may be held up while the input is either pulled to gnd, pulled to some intermediate voltage, or left open- circuit. in all of these cases, the reverse current protection circuitry prevents current flow from output to the input. nonetheless, due to the outs-to-set clamp, unless the set pin is floating, current can flow to gnd through the set pin resistor as well as up to 15 ma to gnd through the output overshoot recovery circuitry. this current flow through the output overshoot recovery circuitry can be significantly reduced by placing a schottky diode between outs and set pins, with its anode at the outs pin. applications information downloaded from: http:///
lt 3042 22 3042fa for more information www.linear.com/lt3042 typical applications 12v in to 3.3v out with 0.8v rms integrated noise 100a in en/uvpg gnd out lt3042 ilim pgfb 453k 4.7f 4.7f v in 12v 5% 200k 4.7f v out 3.3vi out(max) 100ma 49.9k 3042 ta02 33.2k set outs +C 1k low noise cc/cv lab power supply pgfb disabled without reverse input protection pgfb disabled with reverse input protection r set 4.7f 0.47f 4.7f v in out in set lt3042 v out 100a outs pgfb ilim gnd pg en/uv +C 3042 ta12 0.47f 4.7f 1n4148 4.7f r set v in out in set lt3042 v out 100a outs pgfb ilim gnd pg en/uv 3042 ta15 +C 4.7f 0.47f 4.7f r set r iout v in out in set lt3042 v out 100a outs pgfb ilim gnd pg en/uv 3042 ta03 +C v out(max) = ?100 a ??r set i out(max) = ? 125ma ??k ? r iout downloaded from: http:///
lt 3042 23 3042fa for more information www.linear.com/lt3042 typical applications programming undervoltage lockout 4.7f 33.2k 0.47f r en2 110k r en1 49.9k 4.7f v in 4v turn-on 3.4v turn-off out in set lt3042 v out 3.3v i out(max) 200ma 100a outs en/uv ilim gnd pg pgfb 3042 ta04 +C v in(uvlo) = 1.24v 1 + 110k 49.9k ?? ? ?? ? ratiometric tracking 4.7f 0.1f 4.7f 33.2k 4.7f 0.1f 16.9k v in 5.5v to 20v out in set lt3042 v out 3.3vmin load 200a 100a outs pgfb ilim gnd pg en/uv out in set lt3042 v out 5v 100a outs pgfb ilim gnd pg en/uv 3042 ta05 +C downloaded from: http:///
lt 3042 24 3042fa for more information www.linear.com/lt3042 typical applications paralleling multiple devices using ilim ( current monitor ) to cancel ballast resistor drop ultralow 1/f noise reference buffer 4.7f 4.7f 4.7f out in set lt3042 v out = 5v i out(max) 200ma 100a outs pgfb ilim gnd pg en/uv ltc6655-5 3042 ta06 +C 1,2 3,4,5 6,7 10f 49.9k 1k v in 6v 5% 4.7f n = number of devices in parallel r cdc = cable (ballast resistor) drop cancellation resistor r ilim = current limit programming resistor r ballast = ballast resistor ilim = output current limit 4.7f 50m 1f 22f out in set lt3042 100a 100a outs pgfb ilim gnd pg en/uv in pgfb pg en/uv +C 16.5k r ilim 549 r cdc 10 r ilim = 125ma ? k/ilim C r cdc ? n = 549 (for 200ma ilim per regulator) r cdc = r ballast ? 400/n = 10 v out = 3.3v i out(max) = 400ma 549 50m +C 3042 ta13 out lt3042 outs set ilim gnd v in 5v 5% downloaded from: http:///
lt 3042 25 3042fa for more information www.linear.com/lt3042 typical applications paralleling multiple lt 3042 s for higher output current 4.7f 4.7f 50m 4.7f out in set lt3042 100a 100a outs pgfb ilim gnd pg en/uv in pgfb pg en/uv +C 8.25k 50m +C 3042 ta14 out lt3042 outs set ilim gnd 4.7f 4.7f 50m 4.7f out in set lt3042 100a 100a outs pgfb gnd pg en/uv in pgfb pg en/uv +C 453k 200k 49.9k v out = 3.3v i out(max) = 800ma dropout = 350mv 50m +C out pnpq1 pnp q2 pnpq4 pnp q3 lt3042 outs set ilim ilim gnd output noise = ? 0.8v rms 4 = ?0.4v rms v in 5v 5% downloaded from: http:///
lt 3042 26 3042fa for more information www.linear.com/lt3042 ultralow noise higher current regulator with external npn 10f 4.7f 47f 20k 10k 10f 4.7f 750 d44vh10 249k 49.9k out in set lt3042 v out 2v i out(max) 1a 100a outs ilim gnd pg en/uv 3042 ta08 +C pgfb v in 5v 5% ultralow noise higher current regulator with external pnp 10f 4.7f 47f 33.2k 10 0.2 22f d45vh10g 750 150k 49.9k out in set lt3042 v out 3.3v i out(max) 1.5a 100a outs pgfb ilim gnd pg en/uv 3042 ta07 +C v in 5.5v 5% typical applications downloaded from: http:///
lt 3042 27 3042fa for more information www.linear.com/lt3042 typical applications low noise wheatstone bridge power supply 4.7f 33.2k 4.7f 200k 453k 49.9k 4.7f r2 r1 r3 + C r4 v in 5v 5% out in set lt3042 v out : 3.3v and i out(max) : 200ma 100a outs pgfb ilim gnd pg en/uv resistor tolerance bridge psrr noise at v bridge using lt1763 1% 5% 40db 26db 8nv rms 42.5nv rms perfect matching infinite C noise at v bridge using lt3042 200nv rms 1000nv rms C lt1763 noise: 20v rms (10hz to 100khz) lt3042 noise: 0.8v rms (10hz to 100khz) v bridge +C downloaded from: http:///
lt 3042 28 3042fa for more information www.linear.com/lt3042 package description please refer to http:// www .linear.com/designtools/packaging/ for the most recent package drawings. 3.00 0.10 (4 sides) note:1. drawing to be made a jedec package outline m0-229 variation of (weed-2). check the ltc website data sheet for current status of variation assignment 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package 0.40 0.10 bottom viewexposed pad 1.65 0.10 (2 sides) 0.75 0.05 r = 0.125 typ 2.38 0.10 (2 sides) 1 5 10 6 pin 1 top mark (see note 6) 0.200 ref 0.00 C 0.05 (dd) dfn rev c 0310 0.25 0.05 2.38 0.05 (2 sides) recommended solder pad pitch and dimensions 1.65 0.05 (2 sides) 2.15 0.05 0.50bsc 0.70 0.05 3.55 0.05 packageoutline 0.25 0.05 0.50 bsc pin 1 notchr = 0.20 or 0.35 45 chamfer dd package 10-lead plastic dfn (3mm 3mm) (reference ltc dwg # 05-08-1699 rev c) msop (mse) 0213 rev i 0.53 0.152 (.021 .006) seating plane 0.18 (.007) 1.10 (.043) max 0.17 C?0.27 (.007 C .011) typ 0.86 (.034) ref 0.50 (.0197) bsc 1 2 3 4 5 4.90 0.152 (.193 .006) 0.497 0.076 (.0196 .003) ref 8910 10 1 7 6 3.00 0.102 (.118 .004) (note 3) 3.00 0.102 (.118 .004) (note 4) note:1. dimensions in millimeter/(inch) 2. drawing not to scale 3. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.152mm (.006") per side 0.254 (.010) 0 C 6 typ detail a detail a gauge plane 5.10 (.201) min 3.20 C 3.45 (.126 C .136) 0.889 0.127 (.035 .005) recommended solder pad layout 1.68 0.102 (.066 .004) 1.88 0.102 (.074 .004) 0.50 (.0197) bsc 0.305 0.038 (.0120 .0015) typ 4. dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.152mm (.006") per side 5. lead coplanarity (bottom of leads after forming) shall be 0.102mm (.004") max 6. exposed pad dimension does include mold flash. mold flash on e-pad shall not exceed 0.254mm (.010") per side. bottom view of exposed pad option 1.68 (.066) 1.88 (.074) 0.1016 0.0508 (.004 .002) detail b detail b corner tail is part of the leadframe feature. for reference only no measurement purpose 0.05 ref 0.29ref mse package 10-lead plastic msop, exposed die pad (reference ltc dwg # 05-08-1664 rev i) downloaded from: http:///
lt 3042 29 3042fa for more information www.linear.com/lt3042 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. revision history rev date description page number a 6/15 updated text in the second paragraph updated line reg ?v os , change in v os , output noise spectral density specs updated text to clarify fast start-up test conditionupdated text to clarify notes 5, 6, and 7 updated text to clarify note 10 updated graph 10 and graph 12 updated conditions on graph 18 and graph 24 updated conditions on graph 28 updated title of graph 40 updated output voltage section updated fast start-up section modified direct paralleling for higher current section updated typical application circuit ta 02 added equation text to the typical application circuit ta 03 updated typical application circuit ta 06 and ta 13 updated text in the typical application circuit ta 14 and ta 07 updated text in the typical application circuit ta 08 13 4 4 5 6 7 8 9 14, 15 1819 22 22 24 25 26 downloaded from: http:///
lt 3042 30 3042fa for more information www.linear.com/lt3042 ? linear technology corporation 2015 lt 0615 rev a ? printed in usa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com/lt3042 related parts typical application +C 100a in en/uvpgfb gnd out lt3042 ilim pg 4.7f 50m v out 3.3vi out(max) 400ma 3042 ta11 16.5k set outs +C 100a in en/uvpgfb gnd out lt3042 ilim pg 4.7f 50m 10f v in 5v 5% set outs 0.47f parallel devices part number description comments lt1761 100ma, low noise ldo 300mv dropout voltage, low noise: 20v rms , v in = 1.8v to 20v lt1763 500ma, low noise ldo 300mv dropout voltage, low noise: 20v rms , v in = 1.8v to 20v, so-8 package lt3050 100ma ldo with diagnostics and precision current limit 340mv dropout voltage, low noise: 30v rms , v in = 1.8v to 45v, 3mm 2mm dfn and msop packages lt3060 100ma low noise ldo with soft-start 300mv dropout voltage, low noise: 30v rms , v in = 1.8v to 45v, 2mm 2mm dfn and thinsot packages lt3080 1.1a, parallelable, low noise, low dropout linear regulator 300mv dropout voltage (2-supply operation), low noise: 40v rms , v in : 1.2v to 36v, v out : 0v to 35.7v, current-based reference with 1-resistor v out set; directly parallelable (no op amp required), stable with ceramic capacitors; to-220, dd-pak, sot-223, msop and 3mm 3mm dfn-8 packages; lt3080-1 version has integrated internal ballast resistor lt3082 200ma, parallelable, low noise ldo outputs may be paralleled for higher output current or heat spreading, wide input voltage range: 1.2v to 40v, low value input/output capacitors required: 2.2f, single resistor sets output voltage, 8-lead sot-23, 3-lead sot-223 and 8-lead 3mm 3mm dfn packages lt3085 500ma, parallelable, low noise, low dropout linear regulator 275mv dropout (2-supply operation), low noise: 40v rms , v in : 1.2v to 36v, v out : 0v to 35.7v, current-based reference with 1-resistor v out set, directly parallelable (no op amp required), stable with ceramic capacitors; ms8e and 2mm 3mm dfn-6 packages downloaded from: http:///

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